Breadboard Builder — learn to plan
How to use the tools Report a problem / Request a featureThis tool is made for a tablet or a computer. On a phone the board is too small to work on comfortably — the tasks all still run, but come back to it on a bigger screen.
Look at the board, then answer the question beside it: are the two named holes electrically connected? Answer, and the board shows you the copper that makes it true or false.
How to use the tools The planner’s step-by-step guide — the tools are the same. Opens in a new tab ↗Four rules that hold on every stripboard
- A track is a net. The copper runs the whole way across the board, so every leg in that row is joined to every other leg in it. Turning a circuit diagram into a layout is really just giving each net a track.
- Cut every track a chip crosses. A DIL package sits across the tracks, so without a cut between its two rows of pins, pin 1 is joined to pin 14 and pin 7 to pin 8. This is the single most common fault in the verifiers’ reports.
- Adjacent pins are not connected. Two pins side by side on a package are on different tracks. Joining them takes a link wire — and every link is numbered and coloured, with red and black kept for +5 V and 0 V.
- Every gate input must be held. Pull it down to 0 V through a resistor if a switch or sensor feeds it, tie it straight to 0 V if the gate is spare. An input joined to nothing is not a logic 0 — it floats.
Four rules that hold on every breadboard
- A column is a net. The five holes down one column, inside one band, are joined inside the board — a whole rail row is one net too. Turning a circuit diagram into a layout is really just giving each net a column, or a rail.
- A chip straddles the channel. A DIL package sits with one row of pins in the a–e band and the other in f–j, so without straddling it, pin 1 is joined to pin 14 and pin 7 to pin 8.
- Adjacent pins are not connected. Two pins side by side on a package are in different columns. Joining them takes a jumper wire — and every jumper is numbered and coloured, with red and black kept for +5 V and 0 V.
- Every gate input must be held. Pull it down to 0 V through a resistor if a switch or sensor feeds it, tie it straight to 0 V if the gate is spare. An input joined to nothing is not a logic 0 — it floats.
Where to start
Work down the list. Each one is a different way of thinking about the same board — and Fault-finder and Reverse are the two the exam asks for most.
Scroll the board sideways to see the rest of it.
What is joined to what
Testing table
Say what each test point is — for example “Output from OR gate 2” or “Digital high when switch 3 is pressed”. This is saved with your board and copied onto the printed sheet.
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Why this is the answer
What the assessment is looking for
This tool does not give you a mark. It tells you what is joined to what on your board and where that differs from the circuit. The marks for your assignment come from your own hand-drawn layout sheets, judged against the course assessment task descriptors:
- Detailed component layout diagrams — every component shown as its footprint in the hole it occupies, with its item ID, and every track cut marked.
- Use of test points — a numbered test point planned on the layout for each sub-system input and output, before you build.
- Link wires colour-coded and numbered to match your wiring schedule.
The verifiers' reports flag the same faults every year: no cuts between the two rows of pins of an IC, both legs of a component in one track, circuit symbols drawn instead of footprints, and no test points at all.
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Sources & credits
Sources & credits: Board sizes and hole pitch are the real boards used in class (Rapid Electronics 34-0410 and 34-0411, datasheet 583629_v1). The drawing conventions — tracks running across the sheet, a cut marked as an X on the hole, ICs drawn as a labelled rectangle, link wires coloured and numbered — follow the Stripboard Layout Planning Sheet © 2002 Electronics in Meccano (eleinmec.com), which is the sheet used in the workshop; the conventions are reproduced here, not the artwork. The task itself, the fault list and the wording quoted in the feedback come from the National 5 Electronics (C884 75) course and assessment material and the external verification reports, and the linked IC pin-out sheet is the National 5 data sheet X860/75/12 — all © Qualifications Scotland (SQA), reproduced for educational use. Circuits, diagrams and code are original work written for this site, © R Stewart, 2026. Full site credits are on the credits page. R Stewart - October 2026
Sources & credits: The board is a standard 0.1 in prototype breadboard — a 400-point half board (30 columns) and an 830-point full board (63 columns), drawn to the hole pitch and channel width of the boards used in class. The drawing conventions — component footprints rather than circuit symbols, ICs as a labelled rectangle straddling the centre channel, link wires coloured and numbered — are the same ones this site's stripboard tools use, after the Stripboard Layout Planning Sheet © 2002 Electronics in Meccano (eleinmec.com); the conventions are reproduced here, not the artwork. The component list, the fault list and the wording quoted in the feedback come from the National 5 Electronics (C884 75) course and assessment material and the external verification reports, and the linked IC pin-out sheet is the National 5 data sheet X860/75/12 — all © Qualifications Scotland (SQA), reproduced for educational use. Circuits, diagrams and code are original work written for this site, © R Stewart, 2026. Full site credits are on the credits page.
© R Stewart Physics, Electronics and Engineering